DRAM overclockers - Any analysis on tradeoff between memory latency and bandwith

Has anyone come across an analysis of MSFS performance with DRAM overclocks that focus on memory latency over bandwith?

As some may have experienced on the AMD systems, for example, it’s possible to gain significant memory bandwith at the cost of memory latency with unsync’d FCLK ie. DDR5 8000MHz w/ FCLK 2133. The cost for this bonus bandwith is memory latency.

An alternative overclock is to minimize latency at a significant cost to memory bandwith i.e. DDR5 8000MHz FCLK 2000.

Further complicating this analysis would be single CCD vs/ dual CCD CPUs and/or use with x3D CPUs. Has anyone come across MSFS specific datapoints on this topic?

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You might want to watch Debauer’s video on tweaking memory timings.

Thank you. I caught that video earlier this week. Holding Frequency and CL constant, there is large variation in bandwith / latency depending on FCLK settings on the AMD platform.

Being able to trim memory timings can make a huge difference with system responses. I don’t run a DDR5 system, so cannot give a valid opinion. It used to be that latency was king over a few hundred mhz difference in speed on an am4 system. My gut feeling from the videos I have seen on this subject is that the benefit from the transfer increase supersedes latency. Buidlzoid does a lot of videos on DDR5 timings @ https://www.youtube.com/c/ActuallyHardcoreOverclocking/videos

I have a few of his videos marked for when I make the switch myself.